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Shrinking the interconnect wires in a processor is exceedingly difficult because of the requirements of the copper damascene process, an additive process that's used to create the wires.

Ltd. today announced a 90-nm (0.09-micron) logic process for system-on-chip (SoC) designs, featuring effective gate lengths of 70-nm and speed increases of 30% compared to company's current 130-nm ...